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| DS1267 Dual Digital Potentiometer Chip www.dalsemi.com FEATURES Ultra-low power consumption, quiet, pumpless design Two digitally controlled, 256-position potentiometers Serial port provides means for setting and reading both potentiometers Resistors can be connected in series to provide increased total resistance 14-pin DIP, 16-pin SOIC, 20-pin TSSOP packages Resistive elements are temperature compensated to 0.3 LSB relative linearity Standard resistance values: - DS1267-10 ~ 10 k - DS1267-50 ~ 50 k - DS1267-100 ~ 100 k Operating Temperature Range: - Industrial: -40C to +85C PIN ASSIGNMENT VB NC H1 L1 W1 RST CLK GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC NC SOUT W0 H0 L0 COUT DQ 16-Pin SOIC (300-mil) See Mech. Drawings Section VB H1 L1 W1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC SOUT W0 H0 L0 COUT DQ PIN DESCRIPTIONS L0, L1 H0, H1 W0, W1 VB SOUT RST DQ CLK COUT VCC GND NC - Low End of Resistor High End of Resistor Wiper Terminal of Resistor Substrate Bias Voltage Stacked Configuration Output Serial Port Reset Input Serial Port Data Input Serial Port Clock Input Cascade Port Output +5 Volt Supply Ground No Internal Connection RST CLK GND 14-Pin DIP (300-mil) See Mech. Drawings Section VB NC H1 L1 W1 RST CLK NC NC GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC NC NC SOUT W0 H0 L0 COUT NC DQ 20-Pin TSSOP (173-mil) 1 of 12 102199 DS1267 DESCRIPTION The DS1267 Dual Digital Potentiometer Chip consists of two digitally controlled, solid-state potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wiper output. Communication and control of the device are accomplished via a 3-wire serial port interface. This interface allows the device wiper position to be read or written. Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same resolution. For multiple-device, single-processor environments, the DS1267 can be cascaded or daisy-chained. This feature provides for control of multiple devices over a single 3-wire bus. The DS1267 is offered in three standard resistance values which include 10, 50, and 100-kohm versions. Available packages for the device include a 14-pin DIP, 16-pin SOIC, and 20-pin TSSOP. OPERATION The DS1267 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value. These two 8-bit values are written to a 17-bit I/O shift register that is used to store the two wiper positions and the stack select bit when the device is powered. A block diagram of the DS1267 is presented in Figure 1. Communication and control of the DS1267 are accomplished through a 3-wire serial port interface that drives an internal control logic unit. The 3-wire serial interface consists of the three input signals: RST , CLK, and DQ. The RST control signal is used to enable the 3-wire serial port operation of the device. The chip is selected when RST is high; RST must be high to begin any communication to the DS1267. The CLK signal input is used to provide timing synchronization for data input and output. The DQ signal line is used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the DS1267. Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the RST signal input is low. Communication with the DS1267 requires the transition of the RST input from a low state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing diagrams of Figure 9(b)-(c). Data written to the DS1267 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift register contains the stack select bit, which will be discussed in the section entitled "Stacked Configuration." Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value. Bit 1 contains the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position, with the MSB for the wiper position occupying bit 9 and the LSB bit 16. 2 of 12 102199 DS1267 DS1267 BLOCK DIAGRAM Figure 1 I/O SHIFT REGISTER Figure 2 Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper position value and lastly the potentiometer-0 wiper position value. When wiper position data is to be written to the DS1267, 17 bits (or some integer multiple) of data should always be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the register incomplete and possibly an error in the desired wiper positions. After a communication transaction has been completed, the RST signal input should be taken to a low state to prevent any inadvertent changes to the device shift register. Once RST has reached a low state, the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position. A new wiper position will only engage after a RST transition to the inactive state. On device power-up the DS1267 wiper positions will be set at 50% of the total resistance or binary value 1000 0000. 3 of 12 102199 DS1267 STACKED CONFIGURATION The potentiometers of the DS1267 can be connected in series as shown in Figure 3. This is referred to as the stacked configuration. The stacked configuration allows the user to double the total end-to-end resistance of the part and the number of steps to 512 (or 9 bits of resolution). The wiper output for the combined stacked potentiometer will be taken at the SOUT pin, which is the multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer wiper selected at the SOUT output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O shift register. If the stack select bit has value 0, the multiplexed output, SOUT, will be that of the potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, SOUT, will be that of the potentiometer-1 wiper. STACKED CONFIGURATION Figure 3 CASCADE OPERATION A feature of the DS1267 is the ability to control multiple devices from a single processor. Multiple DS1267s can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift register of the DS1267 a bit will appear at the COUT output within a maximum delay of 50 nanoseconds. The stack select bit of the DS1267 will always be the first out the part at the beginning of a transaction. Additionally the COUT pin is always active regardless of the state of RST . This allows one to read the I/O shift register without changing its value. CASCADING MULTIPLE DEVICES Figure 4 4 of 12 102199 DS1267 The COUT output of the DS1267 can be used to drive the DQ input of another DS1267. When connecting multiple devices, the total number of bits transmitted is always 17 times the number of DS1267s in the daisy chain. An optional feedback resistor can be placed between the COUT terminal of the last device and the first DS1267 DQ input, thus allowing the controlling processor to read as well as write data or circularly clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range from 1 to 10 kohms. When reading data via the COUT pin and isolation resistor, the DQ line is left floating by the reading device. When RST is driven high, bit 17 is present on the COUT pin, which is fed back to the input DQ pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the first position of the I/O shift register and bit 16 becomes present on COUT and DQ of the next device. After 17 bits (or 17 times the number of DS1267s in the daisy chain), the data has shifted completely around and back to its original position. When RST transitions to the low state to end data transfer, the value (the same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register. ABSOLUTE AND RELATIVE LINEARITY Absolute linearity is defined as the difference between the actual measured output voltage and the expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolute linearity is given in terms of a minimum increment or expected output when the wiper is moved one position. In the case of the test circuit, a minimum increment (MI) or one LSB would equal 10/512 volts. The equation for absolute linearity is given as follows: (1) ABSOLUTE LINEARITY AL={VO (actual) - VO (expected)}/MI Relative Linearity is a measure of error between two adjacent wiper position points and is given in terms of MI by equation (2). (2) RELATIVE LINEARITY RL={VO (n+1) - VO (n)}/MI Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1267 at 25C. The specification for absolute linearity of the DS1267 is 0.75 MI typical. The specification for relative linearity of the DS1267 is 0.3 MI typical. 5 of 12 102199 DS1267 LINEARITY MEASUREMENT CONFIGURATION Figure 5 NOTE: In this setup, a 2% delta in total resistance R0 to R1 would cause a 2.5 MI error. DS1267 ABSOLUTE AND RELATIVE LINEARITY Figure 6 TYPICAL APPLICATION CONFIGURATIONS Figures 7 and 8 show two typical application configurations for theDS1267. By connecting the wiper terminal of the part to a high-impedance load, the effects of the wiper resistance is minimized, since the wiper resistance can vary from 400 to 1000ohms depending on wiper voltage. Figure 7 presents the device connected in an inverting variable gain amplifier. The gain of the circuit on Figure 7 is given by the following equation: Av = -n/(255-n); where n = 0 to 255 Figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to attenuate an incoming signal. Note the resistance R1 is chosen to be much greater than the wiper resistance to minimize its effect on circuit gain. 6 of 12 102199 DS1267 INVERTING VARIABLE GAIN AMPLIFIER Figure 7 FIX GAIN ATTENUATOR Figure 8 7 of 12 102199 DS1267 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground (VB=GND) Voltage on Resistor Pins when VB=-5.5V Voltage on VB Operating Temperature Storage Temperature Soldering Temperature -0.1V to +7.0V -5.5V to +7.0V -5.5V to GND -40 to +85C -55C to +125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (-40 to +85 VCC=5.0V 10%) C C; PARAMETER Supply Voltage Input Logic 1 Input Logic 0 Substrate Bias Resistor Inputs SYMBOL VCC VIH VIL VB L,H,W MIN 4.5 2.0 -0.5 -5.5 VB-0.5 TYP MAX 5.5 VCC+0.5 +0.8 GND VCC+0.5 UNITS V V V V V NOTES 1 1 1 1 2 DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Current Input Leakage Wiper Resistance Wiper Current Output Leakage Logic 1 Output @ 2.4V Logic 0 Output @ 0.4V Standby Current SYMBOL ICC ILI RW IW ILO IOH IOL ISTBY -1 -1 -1 MIN (-40 to +85 VCC = 5.0V 10%) C C; TYP 22 MAX 650 +1 400 1000 1 +1 UNITS A A NOTES 9 5 mA A mA 7 7 5 4 22 mA A 8 of 12 102199 DS1267 ANALOG RESISTOR CHARACTERISTICS (-40 to +85 VCC = 5.0V 10%) C C; PARAMETER End-to-End Resistor Tolerance Absolute Linearity Relative Linearity -3 dB Cutoff Frequency Temperature Coefficient FCUTOFF 750 SYMBOL MIN -20 .75 0.3 TYP MAX +20 UNITS % LDB LDB Hz ppm/C NOTES 10 3 4 6 CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 7 pF pF (TA=25 C) UNITS NOTES AC ELECTRICAL CHARACTERISTICS PARAMETER CLK Frequency Width of CLK Pulse Data Setup Time Data Hold Time Propagation Delay Time Low to High Level Clock to Output Propagation Delay Time High to Low Level RST High to Clock Input High RST Low to Clock Input High RST Inactive (-40 to +85 VCC = 5.0V 10%) C C; TYP MAX 10 UNITS MHz ns ns ns 50 50 50 50 125 50 ns ns ns ns ns ns NOTES 8 8 8 8 8 8 8 8 8 8 DC 50 30 10 SYMBOL fCLK tCH tDC tCDH tPLH tPHL tCC tHLT tRLT tCR MIN CLK Rise Time, CLK Fall Time NOTES: 1. All voltages are referenced to ground. 2. Resistor inputs cannot exceed the substrate bias voltage, Vb, in the negative direction. 3. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position. Device test limits 1.6 LSB. 9 of 12 102199 DS1267 4. Relative linearity is used to determine the change in voltage between successive tap positions. Device test limits 0.5 LSB. 5. Typical values are for TA = 25C and nominal supply voltage. 6. -3 dB cutoff frequency characteristics for the DS1267 depend on potentiometer total resistance: DS1267-010: 1 MHz; DS1267-050: 200 kHz; DS1267-100: 100 kHz. 7. COUT is active regardless of the state of RST . 8. See Figure 9(a), (b), and (c). 9. See Figure 11. 10. Valid at 25 only. C TIMING DIAGRAMS Figure 9 (A) 3-WIRE SERIAL INTERFACE GENERAL OVERVIEW (B) START OF COMMUNICATION TRANSACTION 10 of 12 102199 DS1267 (C) END OF COMMUNICATION TRANSACTION DIGITAL OUTPUT LOAD SCHEMATIC Figure 10 11 of 12 102199 DS1267 TYPICAL SUPPLY CURENT VS. SERIAL CLOCK RATE Figure 11 12 of 12 102199 |
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